Framing circuit for loran receivers



vJune 2,3, 1959 i E. DURBIN 2,892,188 FRAMING CIRCUIT Foa LoRANREcEIvERs Filed Jan. 12, 195e; 2 sheets-sheet 2 l Mmm/fc A J- l INVENTOREel/YARD D Rza/N ATTORNEY 2,892,188 FRAMING cIRcUrr non LoRAN nawaninuthin, valley stream, NX., assign@ to Sperry Rand Corporation, 'acorporation of Delaware i Application January 12, 1956, serial No.558,736

claims. (c1. 34a-10s) This invention relates generally to crystalcontrolled rate, but varying in their time relation to each otherdepending on the position of the receiver relative to the transmitters.The receiver, such as the loran receiver disclosed in Patent No.2,651,033 to W. P. Frantz, is arranged to measure this time differenceby means of a cathode ray tube indicator and precise timing circuits todetermine the position of the receiver. Operation of the receiverdepends on providing a slow horizontal sweep for the indicator tubehaving the same repetition frequency as the repetition frequency of thereceived pulses. This is achieved in the loran receiver by the provisionof a crystal-controlled oscillator coupled to a divider chain to produceoutput pulses having exactly twice the repetition frequency as thereceived signals. The doubletrequency is required since, in the slowsweep phase of the indicator tube, two traces separated vertically fromeach other but constituting a single continuous time base are provided.

Not only must the sweep voltage be accurately controlled in frequency,but the phase relation between the sweep voltage and the received pulsesmust be controlled so that the received pulses, as'applied to thevertical Adeection plates of the cathode ray tube, may be made to appearat a predetermined position in relation to the time base of thehorizontal sweep appearing on the cathode ray tube. For this purpose, aframing circuit is provided including a manually operated left-rightswitch by means of which the repetition rate of the output of the timingcircuit controlling the sweep may be increased or decreased slightly soas to change the phase relationship between the horizontal sweep and thereceived pulses. As a result the received pulses appearing on thecathode ray tube can be caused toV drift to the right or left and bebroughtinto the proper position along the extent of the horizontaltrace. Y

' `One obvious way of producing a small increase or decrease in therepetition rate of the horizontal sweep is to change the frequency ofthe crystal-controlled oscillator. However, it has been found that it isnot practical to shift the oscillator frequency of a crystal-controlledoscillator asuicient amount to cause an appropriate rate of drift of thereceived signal pulse along the horizontal trace.

1` Another method of increasing or decreasing the pulse repetition rateof the timer output is to alter the division ratio of one of thedividers in the divider chain for one ormore output periods of thedivider. For example, if one divider in the chain having an outputperiod of 1000 microseconds is made to trigger in response to one lessor one more in the number of input pulses from the previous divider inthe chain in just one cycle of the divider during each repetitioninterval of the received loran pulses, afsu'itable rate of drift of thereceived pulse indications Patented June 2 3, 1959 on the cathode raytube screen may be achieved. In existing loran receivers there has beenprovided a divider in the chain including a blocking oscillatorcontrolled by a step counter. After ive input pulses, for example, thestep counter builds up to a voltage sufficient to bias the blockingoscillator conductive, triggering an output pulse. The framing functionhas been achieved heretofore by adding a rectangular voltage pulsehaving a duration equal to the normal output period of the blockingoscillator to the output of the step counter. During the interval of thepulse, the blocking oscillator is caused to re one step earlier or onestep later, depending on the polarity of the rectangular pulse.

Such prior art arrangement has proved unstable and unreliable inoperation where it is desired that the blocking oscillator fire on alater step of the step counter. The reason is that each successive stepin the output of the step counter has a smaller increment of amplitude,so 'that a very slight drift in the cutoif level of the blockingoscillator ltube or change in grid current during the conductive periodof the blocking oscillator may cause the blocking oscillator to continueto fire on the earlier step or may cause it to re on an even later stepof the step counter. In the former case no drift of the received pulseon the cathode ray tube screen Vis produced when the left-right switchis actuated for left drift. In the Ilatter case the rate of drift ismuch too fast for the operator to control. Left framing in such a priorart framing circuit has the eifect of greatly reducing the stable rangeof the blocking oscillator, i.e., the range in which various parametersassociated with the blocking oscillator circuit may change withoutchanging the dividing ratio.

lt is accordingly a general object of the present invention to providean improved framing circuit in conjunction with the timer of a loranreceiver which is characterized by greater stability and reliability andyet is relatively simple and inexpensive in its circuitry.

Another object of this invention is the provision of a new circuit whichaccomplishes the framing function in a loran receiver without reducingthe stable operating range of the associated blocking oscillator dividerin the timer circuit.

These and Vother objects of the invention which rWill become apparent asthe description proceeds are achieved by the provision of a crystalcontrolled timer and framing circuit for a loran receiver comprising acrystal oscillator and a divider chain of blocking oscillators. Meanscoupled to the output of the divider chain produces simultaneously anegative-going rectangular pulse and a positive-going rectangular pulseof predetermined duration, the pulses occurring once each repetitioninterval of the received loran pulses. A differentiating circuitresponsive to the negative-going rectangular pulse produces a negativepulse with an exponentially rising trailing edge coincident with thestart of the negative-going rectangular pulse but of reduced duration. Amanual switch selectively couples the positive-going pulse or thedifferentiated negative-going pulse through a cathode follower to thegrid of the iirst blocking oscillator in the chain. The negative-goingpulse causes the divider to be blocked for a predetermined timeinterval; the positive-going pulse causes the divider to re in responseto one less in the number of input pulses for a predetermined number ofcycles of the divider, whereby the output period Vof the timer, bymanually selecting the positive-going or negative-going pulses isslightly increased or decreased respectively.

For a better understanding of the invention reference should be had tothe accompanying drawings, wherein:

Fig. 1 is a block diagram of the timer circuit and associated framingcircuit for aloran receiver;

Fig. 2 is a'schematic-'diagram of the framingcircuit;

Fig, 3A-E is a series of waveforms of voltages associated with the timerand framing circuit; and

Fig. 4A-C is a series of-curves showing the waveform of thefgridvoltage'on the blocking oscillator controlled bythe frarningcircuit.

The timer and framing circuit of the present invention is hereinafterdescribed as constituting a portion of ya loran receiver, andparticularly, the loran receiver described in the above-identifiedpatent to Frantz. While the present invention appliesparticularly tosuch receiver, it is to be understood that the invention is not limitedto such application butvhas general utility wherever it is desired toselectively increase or decrease the output repetition frequency of acrystal-controlled pulse timer by a small increment, where directcontrol of the controlling oscillator frequency is not practical ordesirable.

Referring to Fig. l, the numeral l indicates generally the timer circuitof a loran receiver, corresponding to the oscillator and divider circuit25 of Fig. 1 in the abovelidentified Frantz patent. Such a conventionaltimer cirlcuit generally includes a crystal oscillator 12 which, forexample, may be a 100 kc. oscillator. The output of the crystaloscillator 12 is coupled through a buffer circuit 14 .to a divider chainincluding five blocking oscillator-type divider circuits indicated at16, 18, 20, 22, and 24. The dividers divide the frequency of theoscillator output voltage in the steps of 5, 4, 5, 5, and 4,respectively, whereby the ten microsecond period of the 100 kc. signalis increased to a 20,000 microsecond period at the output of the divider24.

Thus the output repetition rate from the divider24 is 50 cycles persecond, which is exactly twice the basic pulse repetition rate used inloran of 25 cycles per second. f

The divider chain may be modified to operate at other loran repetitionrates in conventional manner. However, for the sake of simplicity,operation at one basic repetition rate is described by way of example,sincethe principles of operation of the invention can be .appliedequally well for all basic loran pulse repetition rates.

The output from the last divider 24 is coupled to va transient delaycircuit 426, which may be a multivibrator triggered on by the pulsesfrom the divider 24 and triggered off by pulses from the divider 20.Pulses from the transient delay circuit 26 are coupled to the horizontalsweep circuit of the cathode ray indicator (not shown) in the loranreceiver.

The output pulses from the transient delay circuit 26 are also coupledto a square-wave generator, which is preferably an Eccles-Jordantypecircuit, for producing a square-wave output voltage whose frequencyequals one half the repetition frequency of the trigger pulses from thetransient delay circuit 26. A cathode follower circuit 30 couples thesquare-wave output to an A pedestal delay circuit V32. The square-wavegenerator 28, the cathode follower 30, and the A pedestal delay 32correspond respectively to the square-wave generator 51, cathodefollower 53 and A pedestaldelay 57 in Fig. l ofthe aboveidentifiedFrantz patent.

The A pedestal delay circuit 32, as shown by the schematic diagram ofFig. 2, consists of a bistable multivibrator having a pair 'of triodes34 and 36. The squarewave from the cathode follower 30 is coupledthrough a differentiating circuit consisting of a capacitor '38 andresistor 40 to the grid of the triode 36, which islnorrnally conductive.The negative-going pulses derived `by the differentiating circuit fromthe square-wave input cut off the triode 36 and cause the -triode'34 toconduct. As a result the plate potential of the triode 36 rises whilethe plate potential of the triode 34 drops.

The next output pulse from the divider 24) is coupled through adifferentiating'circuit including a capacitor 42 and resistor 44 to theVgrid .of the triode 34. The negative-going pulse cuts the triode 34 oifcausing the triode 36 to conduct again. As afresult the .plate potentialof the 4triode 3.4 rises and the plate potential of the. tflQde 36drops. As shown in Figs. 3C and D, a positive-going rectangular pulse isproduced at the plate of the triode 36 while a negative-goingrectangular pulse is produced at the plate of the triode 34, thedurationof the rectangular pulses being equal to the period of the divider 20,namely, 1000` microseconds. These respective positive-goingiandnegative-going rectangular pulses are coupled from the A pedestal delaycircuit 32 to a framing circuit '446. -As will hereinafter be explainedin detail, the framing circuit 46 utilizes the positive-going andnegative-going rectangular pulses from the A pedestal delay 32 to modifythe action of the divider 16 in the divider chain to increase `ordecrease the period between pulses from the rtransient delay y26 by apredetermined amount, to give the desired drift rate ofthe receivedpulse indica-tions on thecathode ray'tube indicator. This isaccomplished according to the present invention in the following manner.

The framing circuit 46 includes a manually operated spring-centeredswitch 4S. The switch 48 is normally biased toits centered contactposition by spring centering, completing t a .circuit between thesliding contact Iof a potentiometer S0 and the grid of a cathodefollower stage 52. The output from the cathode follower stage is takenacross the cathode resistor 54. and connected to the grid ofa blockingoscillator tube 55 in the divider 16 through .a leakage resistor 56.Thus adjustment of the potentiometer 50 fixes the bias level on the gridof the blocking oscillator tube.

lnFig, 4A is shown a plot of grid voltage on the blocking oscillatortube 55 as a function of time. The blocking oscillator fires wheneverthe grid voltage rises above the cutoiflevel indicated by the dottedline. After firing, the grid drops to a negative value far below cutoffand thenbegins to rise exponentially at a rate-determined by .theR-Ctime constant of the grid leak resistor 56 and the grid capacitor 53.The setting of the bias potentiometer 50 determines the voltage level towhich the grid rises whenthecapacitor 5S is fully discharged. This valueis adjusted so that a desired one of the pulses (indicated at 59m. Fig.4) from the buffer i4 pushes the grid above cutoff, causing the blockingoscillator to fire, for example, on every-fifth input pulse.

The switch 4S in the framing circuit 46 is provided with aLeft contact,indicated as L, and aRight contact indicated as R, vRight and Leftreferring to the respective directions the received signal pulseindication tends to drift `across the face of the cathode ray indicatortube of the .loran receiver. The contact L is connected to the plate ofthe triode 34 of the A pedestal delay 32 through a differentiatingnetwork including a resistor 60 and capacitor 62. The time constant ofthe R-C differentiating network 60, 62 is preferably adjusted so thatthe capacitor-62 substantially discharges in 300 microseconds followingthe negative front edge of the rectangular pulserfromthe plate of thetriode 34. A diode 63 clips the positivepulse normally produced by thedifferentiating circuit at the end of the rectangular input pulse. Thenegative pulse is coupled by the switch 48 when it.is held in the Leftposition through the cathodezfollower 52 to the gridof the blockingoscillator tube 55 in the divider 16.V

Thenegative pulse holds the grid bias of the tube 57S below cutoff forsubstantially 300 microseconds, the .duration-of the negative pulse.Since the input pulsesto the divider .16 have a repetition period of l0microsecondis, the blocking'oscillator tube is not fired runtil the 30thinputpulse. The resulting waveform of the .grid voltage isshownin'Fig.4B. It should be noted that the rise` of thegrid voltageduring leftframing is made more linear bythe constantly decreasing negativerestoration voltageapplied by the v300 microsecond pulse.

Since the Yfirst output from the divider 16 is delayed r from `50microseconds to 300 microseconds bythe framing circuit 46 during theleft framing mode of operation, the nextoutput pulse from the transientdelay circuit 26 is delayed by 250 microseconds. Therefore each sweep onthe cathode ray indicator tube during the Left framing mode of operationoccurs 250 microseconds later than it would in the normal mode ofoperation, so that the indicated loran pulses appear to drift to theleft on the indicator tube face.

In the Right framing mode of operation, the switch 48 connects the gridof the cathode follower to the contact R. The contact R is connected bya coupling capacitor 64 to the plate of the triode 36 in the pedestaldelay circuit 32. Thus a positive-going rectangular pulse of 1000microseconds duration is applied to the grid of the blocking oscillatortube in the divider 16. The amplitude of the applied pulse is adjustedby means of a voltage divider formed by resistors 66 and 68 to changethe blocking oscillator bias suiciently to cause the blocking oscillatortube to lire on the fourth input pulse instead of the iifth input pulse.Thus during an interval of 1000 microseconds for each 4repetitioninterval of the received loran pulses the divider 16 has a divisionratio of 4 instead of 5. As a result the divider 16 puts out liveadditional pulses during the first 1000 microseconds of the basic loranpulse repetition. Since the divider now puts out 25 pulses in the timeit formerly put out 25 pulses, the time it takes to put out 20 pulsesduring the right frame mode of operation is reduced by 250 microseconds.Consequently the period between pulses from the transient delay circuit26 is reduced by 250 microseconds. As a result each sweep in the Rightframing mode of operation occurs 250 microseconds sooner than it wouldin the normal mode of operation, causing the indicated loran pulses toappear to drift to the right on the indicator tube face.

From the above description it will be recognized that the variousobjects of the invention have been achieved by the provision of aframing circuit which modifies the output frequency of the timer circuitwithout impairing the stability range of any of the dividers in thedivider chain. By biasing oli the first oscillator in the chain for anumber of cycles, any instability or change in the blocking oscillatorparameters can not materially aiect the output frequency of the chain.For instance if the blocking oscillator of the rst divider would recoverafter twenty-nine input pulses instead of thirty, this would have littleelect on the drift rate during Left framing.

Since many changes could be made in the above construction and manyapparently widely dilerent embodiments of this invention could be madewithout departing from the scope thereof, it is intended that all mattercontained in the above description or shown in the accompanying drawingsshall be interpreted as illustrative and not in a limiting sense.

What is claimed is:

l, A timer for a loran receiver comprising a crystal controlledoscillator, a divider chain including a rst grid controlled blockingoscillator type divider, a butter coupling the output of the crystalcontrolled oscillator to the rst blocking oscillator, means coupled tothe output of the divider chain for generating a negative-goingrectangular pulse having a duration that is long compared to the periodof the crystal controlled oscillator and that is short compared to theperiod of the divider chain output, means coupled to the output of thedivider chain for generating a positive-going rectangular pulse of thesame duration as and occurring simultaneously with the negative-goingpulse, means including a dilerentiating circuit and clipping circuitresponsive to said negative-going pulse for generating a negative-goingpulse of appreciably longer duration than the period of said crystalcontrolled oscillator but of substantially shorter duration than theduration of the rectangular pulses, and means including a manual switchfor selectively coupling the positive-going rectangular pulse and thenegative-going differentiated pulse to the grid of the blockingoscillator, whereby the blocking oscillator is either biased oi by thenegative-going differentiated pulse or biased by the positive-goingpulse to trigger on an earlier input pulse for a predetermined number ofcycles of the blocking oscillator.

2. A timer for a loran receiver comprising a crystal controlledoscillator, a divider chain including a rst grid controlled blockingoscillator type divider coupling the output of the crystal controlledoscillator to the divider chain, means coupled to the output of thedivider chain for generating a negative-going rectangular pulse, meanscoupled to the output of the divider chain for generating apositive-going rectangular pulse of the same duration as and occurringsimultaneously with the negative-going pulse, means including adifferentiating circuit and clipping circuit responsive to saidnegative-going pulse for generating a negative-going pulse ofappreciably longer duration than the period of said crystal controlledoscillator but of substantially shorter duration than the duration ofthe rectangular pulses, and means including a manual switch forselectively coupling the positive-going rectangular pulse and thenegative-going diierentiated pulse to the grid of the blockingoscillator, whereby the blocking oscillator is either biased oi by thenegativegoing differentiated pulse or biased by the positive-going pulseto trigger on an earlier input pulse for a predetermined number ofcycles of the blocking oscillator.

3. A timer for a loran receiver comprising a crystal controlledoscillator, a divider chain including a rst grid controlled blockingoscillator type divider, a buier coupling the output of the crystalcontrolled oscillator to the first blocking oscillator, means coupled tothe output of the divider chain for generating a positive-goingrectangular pulse that is long compared to the period of the crystalcontrolled oscillator and short compared to the period of the dividerchain output, means for generating a negative-going pulse of appreciablyshorter duration than the duration of the rectangular pulse; and meansincluding a manual switch for selectively coupling the positive-goingrectangular pulse and the negative-going pulse to the grid of theblocking oscillator, whereby the blocking oscillator is either biasedon? by the negative-going pulse or biased by the positive-going pulse totrigger on an earlier input pulse for a predetermined number of cyclesof the blocking oscillator.

4. In a loran receiver having a crystal controlled oscillator anddivider chain including at least one blocking oscillator, means forselectively increasing or decreasing the output frequency of the dividerchain comprising means triggered by the output of the divider chain forgenerating a pair of rectangular pulses of predetermined duration, oneof the pulses being a positive-going pulse and the other being anegative-going pulse, means for diierentiating and clipping thenegative-going rectangular pulse, and means including a switch forselectively coupling the positive-going pulse or the diierentiatednegative-going pulse to a blocking oscillator in the divider chain.

5. In a loran receiver having a crystal-controlled oscillator anddivider chain including at least one blocking oscillator, means formomentarily decreasing slightly the output frequency of the dividerchain comprising means triggered by the output of the divider chain forgenerating a negative-going rectangular pulse, means for diierentiatingand clipping the negative-going rectangular pulse, and means including aswitch for selectively coupling the differentiated negative-going pulseto a blocking oscillator in the divider chain to bias the blockingoscillator oft for a predetermined interval, whereby the output of thedivider chain is delayed.

References Cited in the le of this patent UNlTED STATES PATENTS2,430,570 Hulst Nov. 11, 1947 2,445,361 Mountjoy July 20, 1948 2,487,822McLamore Nov. 15, 1949 UNITED STATES PATENT OFFICE CERTIFICATE OFCORRECTION Patent No. 2,892,188 A June 23, 1959 Edward Durbin A It isherebb'r certified that error appears in the-printed specification ofthe above numbered patent requiring correction and that the said LettersPatent should read as corrected below.

Column 5, line 24, for "25 pulsesn read 2O pulses Signed and sealed this5th day of April 1960.

(SEAL) Attest:

KARL H, AXLINE ROBERT C. WATSON Attesting Oflcer Commissioner of PatentsUNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.2,892,188 June 23, 1959 Edward Durbin It is herebir certified that errorappears in theprinted specification of the above numbered patentrequiring correction and that the said Letters Patent should read ascorrected below.

Column 5, line 24, for "25 pulses" read 2O pulses Signed and sealed this5th day of April 1960.

(SEAL) Attest:

KARL H, AXLINE ROBERT C. WATSON Attesting Officer Commissioner ofPatents

